1. Field of the Invention
The present invention relates to signal transition from ball grid array (BGA) packages to printed circuit board (PCB) intended for high-speed applications. More specifically, the present invention relates to package-board co-design methodology and optimal interconnect architecture between package and printed circuit board layers.
2. Description of Related Art
The ball grid array (BGA) package offers a number of advantages relative to other, older package types (e.g., quad flat pack (QFP) and pin grid array (PGA)), including small size, high input/output (I/O) pin count, improved electrical performance, low profiles, and good yields. The packages can be constructed with a substrate that can be either single or multi-layer. Substrates are fabricated with plastic or ceramic material, electrically conductive traces, and with planes being formed on a surface of each layer of the substrate. The surface of the substrate opposite from the semiconductor die or integrated circuit (IC) contains a plurality of solder balls that are soldered to the pads on a printed circuit board (PCB), thus attaching the package to the board. The semiconductor die is electrically connected to the substrate by either flip-chip (solder bump) interconnect or wire bonding. In both instances, the die is also generally encapsulated by plastic to protect it from the external environment.
One of the key benefits of BGA packaging is the increase of achievable I/O densities compared to older package options. Since BGA packaging places contacts over the entire surface of the chip instead of just around the edges, IC designers can place more I/Os in a given package size while using relatively looser tolerance compared to older peripheral lead types. This offers additional benefits to board designers who are not subsequently constrained to use the fine pitches that are typically necessary for older high-lead count packages. However BGA packaging brings new challenges to the packaging designers, particularly in high-speed IC applications, where the effects of electromagnetic interference (EMI) become extremely important, and BGA I/O densities exasperate this problem.
Signal integrity is another important issue for packages and boards emerging from high-speed transceivers in high-end FPGAs and ICs. Impedance control is critical for package-to-board transitions connecting signals from layer to layer. For example, there are two typical via transitions (via-to-pad) on packages connecting signal traces to board solder pads. These via configurations, the ‘dog-bone’ 120, and via-on-pad 122 configurations, are depicted in FIG. 1. On the board 100, if signal is routed on a top layer, the via-on-pad transition 122 is used and microstrip 123 will be deployed. If signal is routed in the inter-layer stripline 121, the ‘dog-bone’ via transition 120 is used. The via-transitions usually possess very low impedance due to the heavy parasitic capacitance found between a ball and the ground plane. Some package and board manufacturers propose an approach using a thicker substrate layer to reduce parasitic capacitance. This approach enlarges the package and board thickness and has been proved neither practical nor cost effective.
A high-speed BGA semiconductor device having improved electromagnetic interference (EMI) and signal integrity characteristics is desirable. Identifying a suitable electromagnetic shielding approach for use in BGA packaging is critical if the projected benefits of flip-chip technology, including improved EMI and flexible power/ground distribution, are to be fully achieved.